Hello Guys,
Please i need help in designing a current sense amplifier. Pls find attached is the schematic. During a read, the read current is lets say Iread=10uA.
So the differential current Idl-Idlb should be 10uA. I am operating at low voltages and transistors M2 and M4 are always in Linear region since ysel="vdd" during sense amp operation.
My problem is this: I cannot get the differential voltage Vdl-Vdlb to be more than about 5mV during a read operation (Iread=10uA). I tried increasing the DC current in both branches and i always still get only the 5mV differential voltage (Vdl-Vdlb). Please note during read, i attach a current source of 10uA from Vbl to ground (in that direction) in my simulation.

Does anyone know what region of operation the transistors should be in during reset phase (No read current)  and during the read phase? I am not sure if there is such a requirement.

Ps: I am desperately seeking a methodical approach to design this ckt, and haven't been successful in finding any literature that highlights a method.

I think you should try different architecture. Diode connected NMOS  at the bottom do not allow voltage difference.  

tell us what you are trying to do.

Not the circuits you are thinking of using.