Hi there is an excellent discussion on tiedown diodes in
http://www.designers-guide.org/Forum/YaBB.pl?num=1141663850/1#1.
![Smiley Smiley](https://designers-guide.org/forum/Templates/Forum/default/smiley.gif)
However, I can't find the information I needed in that discussion. There are a number of tie down rules in IBM 130 nm process.
1. why n-well needs to be tied down? I know the gate needs tie-down because the thin oxide might be damaged. However I don't understand why n-well needs tie down.
2. what is pTiedown meant for? a pTiedown is p+ diffusion to n-well. However in fabrication, n-well is not connected to any voltage.
3. how p-mos gate is protected? what tiedown diode should be used?
I really appreciate anyone can share some experience on this topic.