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Jul 11th, 2020, 1:06pm
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SMA selection: Inline (Surface Mount) or through hole (Read 3198 times)
BackerShu
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SMA selection: Inline (Surface Mount) or through hole
Jul 19th, 2012, 6:09pm
 
Hello all,

I am designing a PCB to test a CDR circuit which is working at 2.5GHz. The package of the chip has four critical signals, and one at each side of the chip. Two of them are clocks, specifically input clock and output clock with frequency of 2.5GHz, the other two are data signals, including input data and output data with data rate of 5Gb/s.

Since all four of them are kind of high frequency signal and are critical, if I want to minimize all the traces, it comes that the chip should be placed at the middle of the board, which turns out to be 3-inch trace for all of them assuming the board is a 6-inch square and using inline  SMA since it's believed to be better for high frequency signal. Actually, in this sense, it may not be good for getting good performance, since all of them has a fair long trace, 3-inch trace could do bad to jitter performance.

Another option I am thinking of is putting the chip at one corner of the board, and using two inline SMAs and two through hole SMAs to minimize the traces. Here comes another problem about the impedance discontinuity of the through hole SMA, which will cause reflection and also make the jitter performance worse.

So my first question is which option seems to be better and why?

Second question is if the second option is more attracting, which kind of singal, clock signal or data signal, should I chose to use through hole SMA and why?


I couldn't find any useful rule to guide me to do the choice, if you know some rules or some experience on this. Please help.

Any comments will be highly appreciated.
 
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« Last Edit: Jul 19th, 2012, 10:02pm by BackerShu »  
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BackerShu
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Re: SMA selection: Inline (Surface Mount) or through hole
Reply #1 - Jul 19th, 2012, 10:06pm
 
Attached fig is the pin assignment of the chip package. To make the situation clearer. As I underlined in the attached .jpg file, DIN/DIP input data, REC_DATAB/REC_DATA output data, CLK_EX_CML/CLKB_EX_CML input clock, and CLK_OUT_180 and CLK_OUT_0 output clock.
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