Hello everyone.

In some large power consumption circuits, especially Power Amplifier (PA) the current supply is quite high: 10mA ~ 100 mA. In the layout, how wide are the supply wires (vdd, gnd) to provide that current? If the supply wires are too narrow while the running current is too high, it may cause the wires burning, doesn't it? Further more, the PA should provide 10~20 dBm output signal, which also create a large number of AC current flowing in a signal path, then how large should a signal line be to transmit this current ??

The inductor also play as vdd supply for a PA and for example in 0.18 CMOS process the maximum width is 4 um. Is this wide enough to provide 10~100 mA current. To the best of my knowledge, the rule of thumb is 1 um for 1 mA. So how come people can build PA with 30 dBm output power in such process??
Could anyone provide some information? Thank you

If you want to design at such high current, you normally need at least one thick metal layer (2-3 um thick), and copper helps, but I'm not sure if your 0.18um process offers it. Also, you should make sure you get the right design rules from your foundry because 4um doesn't seem very wide. You can also try and get the electrical specifications from your foundry as 1mA/um is pretty low too. In fact it sounds like you are talking about a thin metal. As loose-electron says, you can always run the lines in parallel, but if you only have thin (~0.5um) aluminium to work with you are gonna have a tough time.

I think a transistor driving 100 mA would not be that small, and since the size scales with the current, I doubt it would be a bottle neck. For the output, you can have a slotted inductor, or you could even try power combining.

BTW, the peak AC current handling capability is always higher than the DC current handling capability. I believe this may be more true at RF. There are papers on this.

There are also many papers on CMOS PAs with over 30 dBm of output power (GSM PAs). Why don't you have a look at the layouts.


regards,
Aaron