dear forum,
To increase fmax, lower gate resistance can achived by using multiple fingers, but is there any max limit, like if i use very big is there any effect which increase resisistance.

I know with higher number of fingers, layout become complex and may be some higher paracitic's which can be tuned out.

BR,
Summi.

Dear Aaron,
thanks for the reply. yes i have simulated and not noise figure went up after some time insteed of going down. So i would like to know why it is going up, in theory (or up to my knoeledge) it should keep on decreasing...tell me whats the flaw in my arguement.

Br,
Summi.

The exact reasons are not very clear, but it appears that as you continue to decrease finger length the interconnect capacitance and perhaps the via and/or interconnect metal resistance starts to dominate.

Minimum NF depends on minimizing thermal noise at the input and input referred noise from the output. So, a good clue to why the NF is degrading with further reductions in finger length is to monitor the most significant noise contributors as NF starts to increase. If it is output noise sources that cause the increased NF then a reduction in the maximum gain maybe the reason; otherwise, if the input routing resistance dominates then you will know it is the routing parasitics that dominate the degradation.

Have you looked at changes in the noise summary versus changes in gate length?