First, it isn't a good idea to copy and paste copyrighted material. Quoting and citing the source is fine and appropriate, but cutting and pasting typeset manuscript might fall into the category of "using without permission." Perhaps I am being too picky.

Ok, now on to your question.
The PLL is being used as a frequency multiplier by having a 100MHz reference to a phase/frequency detector to control a 1GHz VCO. The input is 100MHz and the output is 1GHz when you use an integer divider of N=10 to divide the 1GHz signal down to 100MHz to compare it to the reference input.

To understand the 10MHz sideband problem, think about what the condition of the PLL is when it is locked. When locked the output of the phase frequency detector should be zero (ideally). That means that the reference input and the divided VCO signal should be exactly the same at the inputs to the phase/frequency detector.

The 100MHz reference has 10MHz sidebands at -40dBc, so the divided output of the VCO must also have -40dBc sidebands at 100MHz. For this to be true, the output of the VCO must have sidebands that are N times higher than the spurs on the reference.

The same thing happens with noise that is on the reference. It gets multiplied up and dominates the closed loop noise close into the PLL output frequency. Outside the loop bandwidth the VCO no longer tracks the reference noise, so the VCO phase noise dominates at some offset.

So, if the 10MHz sideband was outside the closed loop bandwidth the -20dBc sidebands would roll off with the loop response.

Hope this is clear.