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High Speed Serializer Architecture (Read 423 times)
analog_design
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High Speed Serializer Architecture
Sep 10th, 2012, 6:42am
 
Hi,

I am just confusing with below attached picture. I have some doubt. This is SerDes architecture.

1. Here How 8b/10b and 16b/20b encoded signal is converted into 8:2 multiplexer ?  actually ODD parallel inputs to EVEN parallel outputs

2. Why do we need to generated always ODD and EVEN signal at output of  Serializer ?


If you have any architecture for 8b/10b encoding then, please, suggest me those pipelin topoloy papers.

thank you


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SerDes.png

Warm Regards
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ywguo
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Re: High Speed Serializer Architecture
Reply #1 - Oct 5th, 2012, 3:32am
 
Hi analog_design,

1. Probably that is a typo, 8:2 multiplexer. Smiley I am not sure because I don't know the details and background for your scheme.

2. It is not necessary to generate ODD and EVEN signal at the output of serialier. A reasonable structure comes from your requirement, like speed, and the availabe process, and so on.

Best Regards,
Yawei
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carlgrace
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Re: High Speed Serializer Architecture
Reply #2 - Nov 28th, 2012, 9:11am
 
ywguo wrote on Oct 5th, 2012, 3:32am:
Hi analog_design,

1. Probably that is a typo, 8:2 multiplexer. Smiley I am not sure because I don't know the details and background for your scheme.

2. It is not necessary to generate ODD and EVEN signal at the output of serialier. A reasonable structure comes from your requirement, like speed, and the availabe process, and so on.

Best Regards,
Yawei


Actually I don't think it is a typo.  The internal diagram of the 8:2 serialzer will be the same as the 2-1 that is explicitly shown in the figure.  Really what it means to say is it is 2 parallel 4:1 serializers where the ODD path is only nibble and the EVEN path is another.

You only need the ODD and EVEN signals if you are going to use a DDR scheme.  Otherwise you only need one data path after the coding block.
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loose-electron
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Re: High Speed Serializer Architecture
Reply #3 - Jan 16th, 2013, 8:41pm
 
You are running the flip flops at 1/2 the output data rate (they are slower than just simple gates) and then using Muxes to do the last 2:1 combination at the full speed data rate.
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