Designer’s Guide Community

analog_design

Junior Member

Offline

Posts: 23
INDIA

High Speed Serializer Architecture
Sep 10^th, 2012, 6:42am

Hi,

I am just confusing with below attached picture. I have some doubt. This is SerDes architecture.

1. Here How 8b/10b and 16b/20b encoded signal is converted into 8:2 multiplexer ? actually ODD parallel inputs to EVEN parallel outputs

2. Why do we need to generated always ODD and EVEN signal at output of Serializer ?

If you have any architecture for 8b/10b encoding then, please, suggest me those pipelin topoloy papers.

thank you

Back to top

SerDes.png

Warm Regards

IP Logged

ywguo

Community Fellow

Offline

Posts: 943
Shanghai, PRC

Re: High Speed Serializer Architecture
Reply #1 - Oct 5^th, 2012, 3:32am

Hi analog_design,

1. Probably that is a typo, 8:2 multiplexer.

I am not sure because I don't know the details and background for your scheme.

2. It is not necessary to generate ODD and EVEN signal at the output of serialier. A reasonable structure comes from your requirement, like speed, and the availabe process, and so on.

Best Regards,
Yawei

Back to top

IP Logged

carlgrace

Senior Member

Offline

Posts: 231
Berkeley, CA

Re: High Speed Serializer Architecture
Reply #2 - Nov 28^th, 2012, 9:11am

ywguo wrote on Oct 5^th, 2012, 3:32am:

Hi analog_design,

1. Probably that is a typo, 8:2 multiplexer.

I am not sure because I don't know the details and background for your scheme.

2. It is not necessary to generate ODD and EVEN signal at the output of serialier. A reasonable structure comes from your requirement, like speed, and the availabe process, and so on.

Best Regards,
Yawei

Actually I don't think it is a typo. The internal diagram of the 8:2 serialzer will be the same as the 2-1 that is explicitly shown in the figure. Really what it means to say is it is 2 parallel 4:1 serializers where the ODD path is only nibble and the EVEN path is another.

You only need the ODD and EVEN signals if you are going to use a DDR scheme. Otherwise you only need one data path after the coding block.

Back to top

IP Logged

loose-electron Senior Fellow Offline Best Design Tool = Capable Designers Posts: 1638 San Diego California	Re: High Speed Serializer Architecture Reply #3 - Jan 16^th, 2013, 8:41pm You are running the flip flops at 1/2 the output data rate (they are slower than just simple gates) and then using Muxes to do the last 2:1 combination at the full speed data rate.
Back to top	Jerry Twomey www.effectiveelectrons.com Read My Electronic Design Column Here Contract IC-PCB-System Design - Analog, Mixed Signal, RF & Medical IP Logged