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Analog Mux Design Issue (Read 760 times)
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Analog Mux Design Issue
Sep 25th, 2012, 8:22am
 
Dear reader,

I have been designing neural front end architecture for collecting multiple channel neural data. Each channel/electrode is connected to a preamplifier stage for signal amplification. The outputs from the preampifiers are to be multiplexed. I am stuck with the design of analog multiplexer. Does an 8 to 1 multiplxer involves 8 transmission gates switches with outputs connected together? Any explanations or links? I have attached an image. Somebody asked me following questions and that how i replied:

1.) What do you mean by "the signal gets distorted"?
By signals getting distorted I mean their amplitude and shape is changed. I have a problem designing analog mux. I believe an 8to1 analog mux consists of 8 transmission line switches(pass gates) with their outputs combined together. Actually I am designing a 8 channel neural front end architecture. Neural signals have very low amplitudes and they are required to be amplified before being digitized. In between the neural amplifier and the ADC I have to place a mux so that I can use one ADC for all signals from 8 channels, to conserve area.  

2.) What is the signal (amplitude and frequency)?
The signal input to each pass gate (transmission line gate) is an amplified version of neural signal with amplitude 300mV to 1.3V on a 2.8V supply in 0.5um NSCU technology. Its frequency ranges from 300Hz to 5KHz.  
3.) What is the amplitude of the gate signals?
The amplitude of the gate signal is 2.5V which is higher than  Vmax of input (1.3)+threshold voltage(0.7V)=2V. It is controlling the switch only.
4.) What is the load that the 8 inputs are seeing?  Is the load connected to one input at a time or multiple inputs at a time?
The 8 outputs from neural amplifier which are to be input to mux or more specifically the 8 analog switches of mux see a very low input impedance. The analog transmission gate is made with an NMOS and a PMOS. Their source and drain terminals are shorted together. Input is applied at source with input impedance of (1/gm II 1/gm) while the output is taken at the shorted drain terminal with output impedance: (ro1 II ro2). All the output signals from analog switches are to be combined. Should I adjust aspect ratio of analog switch MOSFETS? or shall i have to design separate circuit for combining outputs correctly.
The load of this combined output is an input terminals of ADC, most probably the gate terminals which turns out to be very high impedance again.
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output_combination.jpg
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aaron_do
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Re: Analog Mux Design Issue
Reply #1 - Sep 25th, 2012, 6:32pm
 
Hi,


if you have distortion only when hooking all the outputs together, then probably your other switches are turning ON somehow. Check the waveforms (1.3 V is not very small). Your calculation of input and output impedance is not really correct since these transmission gates are operating passively. Therefore when turned ON, they should just act like a small resistance in the signal path. Make sure they really are operating passively (VDS = 0) otherwise you might have distortion.

Your idea about how to implement an analog MUX seems ok, but could be improved. Look up literature or datasheets on switches since they are essentially the same thing (SPDT, SP4T, SP8T etc). For instance, the way you are blocking the signal is to turn off the device to make it high impedance. However, you could implement each branch as a T-network, with one shunt branch to ground in the center to short the unwanted signal, and two branches in series which are high-impedance for the unwanted signal. This should result in much better distortion performance.


regards,
Aaron
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Re: Analog Mux Design Issue
Reply #2 - Sep 25th, 2012, 11:01pm
 
Thanks Aron, ur T structured switch concept works! Pass gate switch seemed to be suffering from loading issues. It loaded down its input as it had poor isolation. This one seems to have much better isolation!

Flynn
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EricR
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Re: Analog Mux Design Issue
Reply #3 - Sep 26th, 2012, 2:37pm
 
Make sure the body diodes of the OFF transmission gates aren't clamping the output signal.
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