for nmos cap, when the voltage applied to its gate is very low, for example, the gate voltage is 0.4V for Vthn=0.65v, what is the problem? as i know, the capacitance may be smaller than high gate voltage case. any other influence? such as leakage, parasitic resistor, etc.
besides, for very large resistor(larger than 1M ohm), it can have a large parasitic cap(1pF maybe). in my opinion, the parasitic cap comes from coupling between resistor and substrate, am i right? and how to calculate the parasitic cap for a given large resistor? and any difference for different type resistor?
thanks.