hi,
The two figures shown in the pic here can be used for BG voltageReference  design.
what is the purpose of having that additional resistor in series with pmos curr source?


Thanks,
yvkrishna

sorry, I meant to say that I have noticed designers using both of these for designing BGR and was trying to understand if there is any special advantage of having that additional resistor.

@analog_wiz,

could you elaborate your explanation about psrr, i dont understand the psrr improvement with hi o/p impedance?

Also the o/p impedance should have to be same (assume both cases are designed for same o/p voltage , so the  total resistor whether split/not has to be same.)


I feel that its just for the convenience of trimming one single resistor instead of two.

Thanks,
yvkrishna

I think the output is supposed to be taken at the MOS drain. In that case the resistors can be sized so that they two circuits are nominally identical at DC, but the circuit on the left uses less resistor area.

Here is an example. Say the current splitting resistors on the right circuit are each "R". The circuit on the left would be equivalent if the red resistor was R/4 and the splitting resistors were each R/2. In that case the total resistance for the left circuit would be 1.25*R compared to 2*R for the right circuit, so nearly a 2x savings.

The downside of doing this is that as the current splitting resistors become smaller the circuit becomes more sensitive to the opamp input noise and offset. To see this consider how the performance would change if you had 1 mV offset on the opamp. If the nominal drop across the splitting resistances was 500mV the current in each leg would mismatch about 1/500. However if you cut the splitting resistors in half the drop will be 250mV, and your current mismatch will be ~1/250.

The R/4 and R/2 circuit example I gave is a reasonable trick to cut resistor area, but you have to check the noise and Monte Carlo performance to make sure the benefits aren't outweighed by the noise and offset.

rg

Then for the right one, how about  use two PMOS transistor for the two path instead of only one PMOS transistor.  Regards the opamp offset, is the one PMOS output better than two PMOS transitor? thanks!

mists wrote on Dec 7^th, 2012, 9:04pm:


Opamp offset affects accuracy in two ways: 1) changing the ratio of the right/left legs; and 2) adding directly to the delta-Vbe (PTAT) voltage generated across the resistor that sets the current.

Using two PMOS devices to split the current would essentially eliminate the opamp's contribution to (1), but (2) is a bigger contributor to the overall error. In addition, now you can't draw any current from the output or you will change the ratio of currents.

Thanks everyone for the replies and suggestions.

@RobG,
Thanks, this is what I was looking for, yes mismatch/noise is better for case with larger current split resistor.
as the addnl contributor from amp offset is prop. to  voff/r_split .

@analog_wiz,
I dont have any paper, saw it in some old design.

@mists
May be its fair to compare these 2circuits in the fig here
a) 2 pmos current sources for current split.
b) 1 pmos current source(2x sized) and resistors for current split.

Assuming both are designed for same nominal DC conditions, and major mismatch sources are current mirror, opamp offset.
(a) is better if pmos current mirrors mismatch is small and opamp offset dominates.
(b) is better if mirrors dominate the total o/p referred offset.

because in case (b) thers an additional source of mismatch due to improper current split (with a difference of voff/r_split) even  though the pmos mir mismatch is minimised by the loop.


regards,
yvkrishna