carlgrace wrote on Nov 8th, 2012, 1:17pm:This was a really good article. Takes me back to my earlier days in the trenches of high-volume IC design. I particularly appreciated the Just Good Enough constraint. There was a great line in the book Soul of a New Machine where Tom West says: "Not everything worth doing is worth doing well". Part of the art of good IC design is knowing where a quick-and-dirty job will work and where you really have to stand on your head to meet a hard spec.
To Lex's comment, in my personal experience the dev plan always (usually) includes a test chip with all the knobs and test busses and the like to get your observability. The core functionality and performance of the circuit is verified, the design is centered, and then the most of the test functionality is purged for the final version. In this way you can, to some extent, have your cake and eat it too.
One other point is that Jerry's article was intended for high-volume stuff. For a low-volume ASIC (like the kind I design now) that tunability and testability stays in the chip through production, since the cost driver is NRE, not wafers.
Low volume chips are the exception rather than the rule, so you are lucky enough to operate in a special space.
For low volume stuff I tell the customer to do a PCB instead, some places that doesn't fly so it becomes big buck to do small volume chips.
Soul of a New Machine! That's going back a bit...