dear AMS experts,

I met a problem about the ADE compiler failed when simulating test circuit with verilog A macro. And the problem is the generated netlist lost ahdl_include "***.va".

My simulation environment is:
a. Spectre/MMSIM10.0
b. ADE
c. The switch view includes: veriloga, ahdl

Please kindly advise if any comment, thanks.
Daniel Lai