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YCY

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Questions about PSRR and ground bouncing of VCO
Nov 29^th, 2012, 7:13pm

Hi,

People usually use regulators to reject supply noise,
but can the regulator reject voltage ripples from ground?

I ask so because when I used pxf to simulate the PSRR of my VCO,
I found the gain from GND to VCO output would be much large than Vdd.
Here is simulation result:
(The red line is Vdd and blue line is GND.)

Does it mean the regulator cannot reject the the noise from the ground?
If so, how do we prevent the ground noise from coming into our circuits?
Or do I misunderstanding anything?

Thanks.

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analog_wiz

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Re: Questions about PSRR and ground bouncing of VCO
Reply #1 - Nov 30^th, 2012, 1:13am

It depends on which way your vco is biased: with reference to ground or
with reference to supply(nmos or pmos input vco:so either noise on power or noise on gnd can be detrimental to your vco).A regulator will only
supress depending on its psrr, noise on vdd. For PSRR on ground you will need to have maybe seperate grounds for very low phase noise vco's. Iam
interested in knowing what other methods could be used to supress
ground noise?

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loose-electron

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Re: Questions about PSRR and ground bouncing of VCO
Reply #2 - Nov 30^th, 2012, 1:20pm

This is a messy one - I presume we are talking ring oscillator VCO's?

A handful of things -

VCO is fully differential system.

Pass the signals in and out of the VCO differentially.

Get the ground impedance associated with the oscillator to be low impedance
(metal and substrate contacts)

With all of the above, you should now have an isolated
system with low common mode ground noise.

In practice there will be current sources attached to ground that
will give OK noise rejection at low frequencies.

However, some ground noise can couple though these current sources
at higher frequencies.

So, to minimize this:

Minimize the geometry of the ground connected current sources.
(Reduces C at the expense of matching!)

However you can't reduce the current source size to nothing.
(matching suffers too much)

So you are left with a current source to ground with an equivalent
capacitance in parallel with the current source.

Reducing the effects of that?

A small amount of series resistance above the current source and below the differential
pair often will help. The resistance parasitic (small W, L sizes) to ground is less than the
current source parasitic.

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Jerry Twomey
www.effectiveelectrons.com
Read My Electronic Design Column Here
Contract IC-PCB-System Design - Analog, Mixed Signal, RF & Medical

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raja.cedt

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Re: Questions about PSRR and ground bouncing of VCO
Reply #3 - Dec 2^nd, 2012, 4:59pm

hello ycy,
yes you are correct, normal regulator(opamp with pmos load) cann't suppress noise from ground. I would say you have to simulate pssr from vdd to output as well as psrr from gnd to output, which is more informative rather including vco into the picture any this is not main point to discuss. If you want to protect your circuit from gnd noise try to reduce the decap (which is good for vdd noise reduction but bad for gnd noise). If you have time to implement new architecture refer thsi pap..

http://web.engr.oregonstate.edu/~hanumolu/PAPERS/jssc_dec_06.pdf

@ loose elctron: why adding a small resister will solve problem at lower frequency, i guess gnd noise coming from the second stage not through first stage opamp.

Thanks,
raj.

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YCY

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Re: Questions about PSRR and ground bouncing of VCO
Reply #4 - Dec 5^th, 2012, 2:58am

Hi all,

Thanks for your responses.
I think I need to describe more about my VCO:

1. My design is an nMOS cross-coupled LC-VCO.
� �I cannot have a separate gnd for VCO because the pin number is limited.
� �The measured spurs are large (~-50dBc @ 40 MHz) and cannot be suppressed with a narrower PLL bandwidth.
� �So I think the spur may coming into the VCO through Vdd or gnd.

2. The supply voltage is very low (1.05V). After the regulator I have almost no headroom for a current source attached to ground.
� �Is there any method to suppress ground noise with fewer voltage consumption?

3. I simulated the gnd psrr in two different cases:

�

In case I, the gain from gnd to VCO output is much greater than vdd. (The simulation result is post in the beginning)
However in case II, the gain from gnd is much smaller than vdd.
I am confused which result is correct?

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loose-electron

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Re: Questions about PSRR and ground bouncing of VCO
Reply #5 - Dec 18^th, 2012, 12:40pm

raja.cedt wrote on Dec 2^nd, 2012, 4:59pm:

hello ycy,
yes you are correct, �normal regulator(opamp with pmos load) cann't suppress noise from ground. I would say you have to simulate pssr from vdd to output as well as psrr from gnd to output, which is more informative rather including vco into the picture any this is not main point to discuss. If you want to protect your circuit from gnd noise try to reduce the decap (which is good for vdd noise reduction but bad for gnd noise). If you have time to implement new architecture refer thsi pap..

http://web.engr.oregonstate.edu/~hanumolu/PAPERS/jssc_dec_06.pdf

@ loose elctron: why adding a small resister will solve problem at lower frequency, i guess gnd noise coming from the second stage not through first stage opamp.

Thanks,
raj.

No, the resistor helps at higher frequencies.

Model the ground rejection with without the resistance.

Instead of a Cds capacitance connecting the diff pair to ground you are changing it into a R-Cds structure.

It helps with ground noise rejection somewhat, but you can not go too big on it.

(If I recall, I did a noise optimization of this once and for a particular case 20 ohms was about right, but that depends on the noise frequency and the Cds of the current source)

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Jerry Twomey
www.effectiveelectrons.com
Read My Electronic Design Column Here
Contract IC-PCB-System Design - Analog, Mixed Signal, RF & Medical

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loose-electron

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Re: Questions about PSRR and ground bouncing of VCO
Reply #6 - Dec 18^th, 2012, 12:45pm

YCY wrote on Dec 5^th, 2012, 2:58am:

Hi all,

Thanks for your responses.
I think I need to describe more about my VCO:

1. My design is an nMOS cross-coupled LC-VCO.
� �I cannot have a separate gnd for VCO because the pin number is limited.
� �The measured spurs are large (~-50dBc @ 40 MHz) and cannot be suppressed with a narrower PLL bandwidth.
� �So I think the spur may coming into the VCO through Vdd or gnd.

2. The supply voltage is very low (1.05V). After the regulator I have almost no headroom for a current source attached to ground.
� �Is there any method to suppress ground noise with fewer voltage consumption?

3. I simulated the gnd psrr in two different cases:

http://img96.imageshack.us/img96/5842/simnp.png�

In case I, the gain from gnd to VCO output is much greater than vdd. (The simulation result is post in the beginning)
However in case II, the gain from gnd is much smaller than vdd.
I am confused which result is correct?

Can you put a common mode inductor below the oscillator? That takes no voltage headroom but is expensive in terms of space.

Filtering out the ground noise requires impedance, and it sounds like you do not have the voltage headroom for active circuits.

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Jerry Twomey
www.effectiveelectrons.com
Read My Electronic Design Column Here
Contract IC-PCB-System Design - Analog, Mixed Signal, RF & Medical

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