SA,
when I perform an stb analysis in cadence for PLL model I have made using verilog-a i get (nan ) in all the fields of stability
I am putting the Iprobe between the VCO block & the divider block & I am selecting it as a probe of instance
I am sure there is some thing wrong but I do not know which is wrong

Optinmized,

 You have not provided enough information to comment is detail. Some
observations assuming this comment is based on a time domain model:
1) A PLL is a fairly complex system, how are going about defining an
   operating point? It would probably need to be based on a periodic
   steady state. However, unless the design is an Integer-N PLL with a
   low divide ratio, then this is not possible.
2) If you can get a periodic steady-state, then the question becomes how
   are you modeling the components in the PLL. Unless their contribution
   to excess is correctly modeled, then it is unlikely that stability
   analysis will return the results you are looking for.

                                                                Best Regards,

                                                                    Sheldon