Hi，

I am desig a PLL for an ADC, and the ADC has spec of clk jitter;

from PLL design I can get the PLL out phase noise L(f)

int(L(f))------>can get phase jitter, namely edge-to-edge jitter;

does this phase jitter is the sampling clk jitter i need to meet?

from ADI app note MT-008, the clk time jitter is the phase jitter ;

but
http://www.designers-guide.org/Forum/YaBB.pl?num=1260769814

give different idea

anybody know the exact answer?