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Digital sizing for RF: PFD (Read 936 times)

mixed_signal Senior Member Offline Posts: 183	Digital sizing for RF: PFD Dec 30^th, 2012, 10:41pm Hi, I am designing a 2.4Ghz integer N PLL with 1Mhz reference. While sizing inverters for RF is there any special considerations in sizing inverters/gates , I mean PMOS to NMOS ratio etc. I have sized for highest speed i.e. beta=2. Although power consumption is also a concern for me
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raja.cedt Senior Fellow Offline Posts: 1516 Germany	Re: Digital sizing for RF: PFD Reply #1 - Dec 31^st, 2012, 1:02am hello, though it is RF application, pfd will work as digital block. Make sure that Inverter has very low rise time (it may impact dead zone, i am not so sure). But beta around 2 might cause problems, but i have idea abut you technology so be care full while choosing beta, in earlier my design beta around 3. Thanks, Raj.
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mixed_signal Senior Member Offline Posts: 183	Re: Digital sizing for RF: PFD Reply #2 - Dec 31^st, 2012, 10:15am Hi raja.cedt, I am using IBM 130nm tech. So, how beta should be selected 1) symmetric swing i.e. equal rise and fall time i.e beta=3.5 etc. OR 2) Highest speed beta=2 Thanks!
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raja.cedt Senior Fellow Offline Posts: 1516 Germany	Re: Digital sizing for RF: PFD Reply #3 - Dec 31^st, 2012, 1:00pm use 3.5. What do you mean by high speed beta? Thanks, Raj.
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mixed_signal

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Re: Digital sizing for RF: PFD
Reply #4 - Dec 31^st, 2012, 5:58pm

High speed beta means that the ratio for which sum of tpLH + tpHL is minimum.

To get an intuitive appeal: If you design a ring oscillator with inverters sized for minimum delay then the oscillator will have the highest frequency.

Since in my RF design both speed and power is a concern, I was wondering if there is some optimal sizing

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