Virvasav
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Posts: 9
Kolkata, India
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Hi, While designing a LC VCO with MOS cap as varactor, I face the problem in top level of PLL. As capacitor is varying with the voltage difference between two nodes, so, the output is asymmetrical and it affects the variation in input node of VCO, i.e., control voltage. These varaition in control voltage creates a problem of jitter at the top level of PLL. Please give me the solution, how to deal with this problem ????
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