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Virvasav

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Kolkata, India

Effect of varying capacitor in LC VCO
Jan 02^nd, 2013, 9:27pm

Hi,
While designing a LC VCO with MOS cap as varactor, I face the problem in top level of PLL. As capacitor is varying with the voltage difference between two nodes, so, the output is asymmetrical and it affects the variation in input node of VCO, i.e., control voltage. These varaition in control voltage creates a problem of jitter at the top level of PLL. Please give me the solution, how to deal with this problem ????

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raja.cedt

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Germany

Re: Effect of varying capacitor in LC VCO
Reply #1 - Jan 3^rd, 2013, 1:38am

Hello,
can you describe the Question clearly??? Why you didn't catch VCO problem at that level?? If i understood correctly, you are facing problem with variable capacitance not only with dc but also with swing. This is a minor effect. Please show me the plot.

AGAin i didn't understand how swing is effecting your input (what is input for vco, control voltage?)

Thanks,
raj.

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Virvasav New Member Offline Posts: 9 Kolkata, India	Re: Effect of varying capacitor in LC VCO Reply #2 - Jan 3^rd, 2013, 1:54am Hi raj, Thanks for the reply. I have designed a wide range LC VCO, but when I am using this VCO in the PLL loop, my control voltage gets coupled with the output. This coupling causes jitter at the output. If question is not understood, the I will attach the waveforms of the output and schematic. Thanks
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raja.cedt Senior Fellow Offline Posts: 1516 Germany	Re: Effect of varying capacitor in LC VCO Reply #3 - Jan 3^rd, 2013, 2:24am yes..please attach. I understood man, but it will at 2nd harmonic. but why you went to top level you could have catch this problem at vco level and finally this will give spurs at 2nd harmonic of the carrier frequency not jitter.
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Virvasav New Member Offline Posts: 9 Kolkata, India	Re: Effect of varying capacitor in LC VCO Reply #4 - Jan 3^rd, 2013, 3:12am Hi raj, I am attaching schematic (architecture) of LC VCO, the output of PLL (outp & outn), also the tuning voltage(vtune). Thanks
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raja.cedt

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Posts: 1516
Germany

Re: Effect of varying capacitor in LC VCO
Reply #5 - Jan 3^rd, 2013, 5:00am

hello,
Read this pap, you will understand.

Frequency Dependence on Bias Current in 5-GHz
CMOS VCOs: Impact on Tuning Range and
Flicker Noise Upconversion

Basically vco two nodes fundamental harmonics are out of phase and 2nd harmonic are in phase. This 2nd harmonic will coupled to control voltage, hence spurs but this spurs will be filters since they very far from loop BW.

What i didn't understand is how did your jitter impacted by this problem. Take FFT of the control voltage and see how below the 2nd harmonic from the ref frequency.

Thanks,
Raj.

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Virvasav New Member Offline Posts: 9 Kolkata, India	Re: Effect of varying capacitor in LC VCO Reply #6 - Jan 3^rd, 2013, 8:49pm Thanks, I think it will help.
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Virvasav New Member Offline Posts: 9 Kolkata, India	Re: Effect of varying capacitor in LC VCO Reply #7 - Jan 7^th, 2013, 11:25pm Hi, You are talking about jitter. Is this a random jitter or deterministic. However, when control voltage changes it cause deterministic jitter at the output.
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