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The Designer's Guide Community Forum › Design Languages › Verilog-AMS › sformat equivalent in Verilog-A

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sformat equivalent in Verilog-A (Read 2197 times)

ShawnR New Member Offline Posts: 1	sformat equivalent in Verilog-A Jan 03^rd, 2013, 6:48am I am trying to convert a real to a string in Verilog-A. In Verilog I would use sformat. Any ideas how to do it in Verilog-A? Shawn
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Geoffrey_Coram Senior Fellow Offline Posts: 1999 Massachusetts, USA	Re: sformat equivalent in Verilog-A Reply #1 - Jan 7^th, 2013, 5:53am What do you intend to do with the string afterwards? Most simulators that support Verilog-A allow you to $strobe or $display with the usual C-style formatting (%e or %f), if you want to output the string. Many simulators also support $fstrobe.
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