fig1

Hello,
There is some thing went wrong in calculations or loop Bandwidth higher than Gadner limit  (Fref/10). Show me loop parameters like Icp, Kvco and filter element.

Thanks,
Raj.

Hello mixed_signal,

How do you know the PM in your real model? (Not from the calculation.)
Did you check the actual loop delay?

Hi raja.cedt,
I cant play with current since I have low power constraint.
current is inversly prop with R so to reduce R from 500k to 50k I have to increase current to 500uA which is not possible.

Hi backer,
I am talking abt PM from calculation

Then you have only one option, redesign VCO. Looks like you have very small Kvco, with generic vco architectures (mainly ring VCO) you could get Kvco min 1Ghz/V. Try this.

If you can't do this then go for dual loop pll(which is having many degree of freedoms) rather conventional loop filter

Thanks,
raj.

Hello,
Looks like some thing seriously went wrong in the filter design, that's why some weird start-up, it is dangerous some times just because vctl is saturating and may turn of charge pump. But frequency settling looks okay, though there is some ringing (some part is cycle slipping). Did you modified your charge-pump current (as i suggested earlier), though you don't have power margin just try that (some how reduce the BW) and see the response.  Since you have 33.33khz BW, your loop should settle in 4*tau, which is around 120us but your settling looks pretty faster than this.

Even if you have any problem with settling, due to less Phase margin magnitude response might have few db peaking which amplifies your jitter, so it all depends on which kind application you are targeting.