Shown is the current summing bandap here, how to estimate the mid range psr for this circuit analytically?
Error amp used has nmos i/p pair and pmos mirror loaded. Amp o/p pole is the dominant pole of the system.

I expect(and see) usual plot like a simple LDO (with nmos i/p stage error amp and pmos pass trans at o/p) where the  PSR first rises at the 3dB freq of the Loop and then saturates at about the  ugb of the loop.

Can we use similar approach here also? what would be the rough estimates for zero and the pole for this psr plot of bgr?
Does this mid-freq psr depend on the any capacitor after once the gain,ugb of the loop is fixed?


The well known solution to improve the mid freq (rather the worst psr across freq range)is  by adding a cap at the o/p of bgr which simply acts as a filter.(which comes at the cost of slowing down the  bandgap)

Is there any alternative method to control/improve the worst psr (acorss all freq range) for this circuit? (may be intrinsically if we clearly know what limits it)


Thanks,
yvkrishna