There are 2 options of 14-bit DAC on a full range of 1.2V that we are trying to implement:

a) Using 8 bits on a R+MOS DAC (5 bits on RDAC and 3 on MOSDAC) and other 5 bits (MSBs) on the capacitive DAC. Last bit (MSB) is a sign bit. S/H circuit is used to charge the output.
b) Using 14 bit R+MOS DAC (8 bits on RDAC and 6 bits on MOSDAC).

From bench data of past performances, option a is not much better than option b. Theoretically, cap DAC is supposed to improve INL due to better matching and reduce current and area consumption. However, both DNL and INL is similar for both option a and option b. Area and current is also similar.

I will be grateful if you could give your views on following questions:
1. Is it better to implement Capacitive DAC on LSB and RDAC on MSB for option a?
2. kT/C noise analysis gives me a value of noise to be 100uV for 400fF cap. But LSB itself is 72uV. Will increasing the size of cap increase performance?
3. Any other architecture that we can try which will be good for high performance, high resolution DAC?

Thank you!