hello,
Could you provide some more details like control voltage waveform,due to asymmetry in VCO two voltages, you will have even harmonics on the control voltages which intern gives spurs at even multiples of carrier frequency (of course which is not a big problem due to lower BW of the loop). Coming to dc component (as you pointed out 'low frequency') which might cause reference spurs at reference frequency, but this can't happen with a good design. So check you schematic, is there any schematic entry error or some thing else....

Thanks,
raj.

Hello,
How can you say "there is no proper charging and discharging of control voltage". Looks like some strange problem and can't be root cause if there is no waveforms. So please show me control voltage waveform and vco output's.

Thanks,
Raj.

Dear looselectron,

what's your opinion on this ripple on the control voltage, i think i wont be a problem as i posted earlier, but i don't know how to observe in simulation just because while designing VCO i would rather connect a voltage source at the control voltage so no ripple at the same time in the PLL locking simulations again due to filtering nature. So i am surprised who he observed this effect.

Thanks,
Raj.

Hi all,

Sorry for the late response.
Actually I am not facing any problem in the VCO level but while using this vco in top level it creates the problem.
For your assistance I am attaching the a test circuit diagram and plot of vtune. The thing to look here is that, I have fixed the control voltage at 0.5 V but while low pass filtering it I found that control voltage settles at the 0.63 V, it means some low frequency (or dc) current flow into the vco.
I think now you got my problem. Thanks.

Virvasav