raja.cedt wrote on Jan 22nd, 2013, 11:37am:Dear looselectron,
what's your opinion on this ripple on the control voltage, i think i wont be a problem as i posted earlier, but i don't know how to observe in simulation just because while designing VCO i would rather connect a voltage source at the control voltage so no ripple at the same time in the PLL locking simulations again due to filtering nature. So i am surprised who he observed this effect.
Thanks,
Raj.
Raj - I think more information is needed before you can say anything. A lot of PLL simulations are faulty due to errors in math resolution and similar.
I usually will do the PLL part by part (like you describe with the VCO control voltage fixed and open loop) and then when all of thats good do closed loop simulations at the behavioral level (Matlab-Simulink or Verilog AMS)
Jerry