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cadence forum (Read 3702 times)
satya391
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cadence forum
Jan 23rd, 2013, 8:56am
 
How to measure delay of ADC designed in cadence spectra ?
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Geoffrey_Coram
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Re: cadence forum
Reply #1 - Jan 24th, 2013, 11:30am
 
You're going to have to provide more information.  For example: what kind of adc?  I'm not sure your question even makes sense for a sigma-delta converter.
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If at first you do succeed, STOP, raise your standards, and stop wasting your time.
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satya391
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Re: cadence forum
Reply #2 - Jan 28th, 2013, 5:35am
 
Thank you  for reply
I have designed a 6 bit Flash ADC in cadence spectra.
How to measure maximum speed of ADC.
Also how to find INL,DNL plot.
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sheldon
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Re: cadence forum
Reply #3 - Jan 29th, 2013, 5:49pm
 
Satya,

 Assuming you have access to Virtuoso, IC61x, in the ahdlLib are
example components to measure INL and DNL of a data converter.
The examples are for 8 bit data converters, you will need to change
the variables for your designs and update the pins.

  I am perplexed by your request for a delay measurement. While
delay can be measured for data converter, performance is usually
unrelated to data converter delay. You might find it more useful to
perform a parametric sweep of the clock frequency and measure
the data converter parameters: THD, SFDR, SNDR, ... and decide
based on the performance across frequency what the maximum
performance is. All these functions are available in the IC615
version of ViVA when using the spectrum function.

                                                                     Best Regards,

                                                                         Sheldon  
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satya391
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Re: cadence forum
Reply #4 - Jan 30th, 2013, 3:30am
 
Thank you for your essential guidance.
Sir,Actually I am working on TIQ ADC and don't give clk so how to know sampling rate (like 1Gs/s).please help me.
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