I currently have a spectre dvc_model.scs file that looks like this:
Code:library mylib
section SLOW
ahdl_include "dvc_model.vams"
endsection SLOW
section NOM
ahdl_include "dvc_model.vams"
endsection TYP
section FAST
ahdl_include "dvc_model.vams"
endsection FAST
endlibrary mylib
I would like to do this purely in Verilog-AMS so that when I use the config view in Virtuoso, it netlists properly.
Is it possible to do this in Verilog-AMS? I can't find anything regarding sections in the manual.
Thanks,
Chris