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biasing of PA (Read 3207 times)
mixed_signal
Senior Member
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Posts: 183
biasing of PA
Feb 09
th
, 2013, 8:12pm
What is the best way to generate bias VB1, VB2, VB3?
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classA_bias.jpg
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rfidea
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Posts: 159
Europe
Re: biasing of PA
Reply #1 -
Feb 10
th
, 2013, 5:21am
My first thought was to use current mirrors. For example, use a diode connected reference transistor to bias nodes V1 and V3. The scale the nmos devices to get wanted current. The V2 can be biased by a CMFB loop sensing the dc voltage of drain voltage of the pmos transistor.
One question about biasing the output stage although. If the current is high, maybe a mismatch of a current source can be severe and the current will not be what you want. Maybe the output current should be sensed by a small resistor to ground or vdd and then using feedback. Of course a rail-to-rail amplifier is needed but those can be designed.
Some ideas... Maybe others has other ideas
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Erez_Sarig
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Re: biasing of PA
Reply #2 -
Feb 10
th
, 2013, 7:11am
Enjoy...
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mixed_signal
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Posts: 183
Re: biasing of PA
Reply #3 -
Feb 10
th
, 2013, 11:18am
Thank you rfidea and Erez_Sarig!
Erez_Sarig:
I cant bias first stage using that. It consumes more power even as class AB. I have to independently bias NMOS & PMOS to be power efficient and operate as class AB
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Erez_Sarig
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Re: biasing of PA
Reply #4 -
Feb 10
th
, 2013, 11:37pm
Enjoy2...
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aaron_do
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Re: biasing of PA
Reply #5 -
Feb 12
th
, 2013, 6:58pm
Hi,
I agree with Erez_Sarig's use of feedback to bias the first stage, but if you want to maximize the output swing of the first stage, you may want to compare the output DC voltage with VDD/2 using a feedback amplifier.
regards,
Aaron
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there is no energy in matter other than that received from the environment - Nikola Tesla
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