My first thought was to use current mirrors. For example, use a diode connected reference transistor to bias nodes V1 and V3. The scale the nmos devices to get wanted current. The V2 can be biased by a CMFB loop sensing the dc voltage of drain voltage of the pmos transistor.

One question about biasing the output stage although. If the current is high, maybe a mismatch of a current source can be severe and the current will not be what you want. Maybe the output current should be sensed by a small resistor to ground or vdd and then using feedback. Of course a rail-to-rail amplifier is needed but those can be designed.

Some ideas... Maybe others has other ideas

Thank you rfidea and Erez_Sarig!

Erez_Sarig:

I cant bias first stage using that. It consumes more power even as class AB. I have to independently bias NMOS & PMOS to be power efficient and operate as class AB

Hi,


I agree with Erez_Sarig's use of feedback to bias the first stage, but if you want to maximize the output swing of the first stage, you may want to compare the output DC voltage with VDD/2 using a feedback amplifier.


regards,
Aaron