Hi Guys,

I have a rail-to-rail output opamp with class-AB output, which is shown in the following picture. I am confused that its rise time is much bigger than its fall time. The opamp is configured into a non-inverting 2X gain mode.

Any comments are appreciated.

Yawei

How do the voltage nodes 'push' and 'pull' look like?

You Amp is not working in saturation so the Class AB is not the issue here. you apply a large signal.
So the reason should be due to NMOS / PMOS output drivers which do not have same resistance.
PMOS is not 2X MOS but more 2.5-2.7MOS.

Monitor the gates and see they are at maximum opening.

Erez Sarig

I don't read schematics sidewise but I see a few clues.

1) the first pulse is different than the rest so something is probably becoming debiased.
2) The tail current source seems to be very large.
3) The slow rise, fast fall would be consistent with capacitance on the tail current source stealing all the current from the diff pair. Be aware that the diff pair bulk connection to the tail node will add even more capacitance and it isn't modeled.

I'd try it in inverting configuration so that the diff pair isn't getting jerked around. (I guess you could make the tail current source ideal). If it works then I'd guess the capacitance on the tail node is stealing your bias current.

Hi Guys,

The primary factor that results in the slow rise time is the load, a feedback network consisting of 2 resistors. Please look at the test bench for the amplifier step response on the left of the following picture. Is it a wrong choice to drive such a load with class-AB output driver?

The rise time reduces a lot if I change to the test bench on the right of the following picture.

Best Regards,
Yawei

Hi RobG,

You are correct. The load has nothing to do with the rise/fall time. I made a mistake when I compared two configurations. The output step of the unity gain feedback was half the amplitude of the step of the gain=2 feedback. The supply is single 3.3V.

Quote:


The rise/fall time becomes more balanced when I replace the tail  current source with an ideal current source. Then I tried to reduce the capacitance of the source node of the diff. pair. It does not improve much.

I found the tail current decreases by half when the inp/inm increases. It is curious because that the Vds is still much bigger than Vdsat.

In the following picture, net016 is the source of the differential pair, M3/s is the tail current, M1/S and M2/S is the source current of each MOS transistor of the differential pair.

net016 increases by near 1.3V, so the parasitic capacitor must have steal some tail current. But why M3/S decreases by almost half?

Thanks very much for your help.
Yawei

ywguo wrote on Feb 26^th, 2013, 4:01am:

OK, I've done that too. The output going all the way to the bottom rail is also going to cause problems so you need to reduce output swing.

Capacitance doesn't seem to be your issue; it sounds like you need to make M3 longer to increase the impedance (or make it a cascode device).

If there is a way to reconfigure the system to use the opamp in inverting mode it is going to perform a lot better since the tail current source will see the same voltage.

Hi RobG,

The following is comparison of the original design, the half-size tail current and ideal tail current. The red line is the step response of the original design. The purple line is the step response of the opamp with half-size tail current. The black line is the step response of the opamp with ideal current source.

The purple line improves compared to the original design. I will try to improve the tail current source further.

Thank you very much.

Yawei