mixed_signal wrote on Feb 12th, 2013, 11:45pm:1. How do I get fair estimate of parasitic cap Cpar (bond pad+bond wire+ package pad+ pcb)
I can try to answer the first question.
You can get an accurate estimate of the on-chip parasitic capacitance using parasitic extraction software (StarRC, QRC, Calibre XRC, F3D,...). The on-chip parasitic capacitance is caused both by pad capacitance, and by interconnects capacitance (in your case, source/drain interconnects capacitance, and maybe source/gate and drain/gate).
For the off-chip capacitance, you can probably use some package and PCB simulation software, but its use requires some expertise. You can probably do some hand estimations of the wirebond and PCB capacitance.
Max
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