carlgrace wrote on Jul 22nd, 2014, 10:45pm:He's not saying "make it huge", he's saying put in enough design margin (where that can be making devices larger but also putting in "chicken bits" such as offset aligners, bias programmability and the like) that the chip will still work even with worst case process.
Like Jerry says, it is usually obvious where the danger zones are in a given design. Add a bit of extra margin to those areas and sleep better.
Agreed!
Lets take the case of some big SOC where the ADC/DAC/PLL/Whatever occupies 5% of the chip area and the other 95% of the chip is a big pile of digital verilog.
2 things will kill this IC:
1 - defect density statistics in the digital parts.
2- analog parts not operating within spec (noise, offset, whatever)
Defect density is pure statistical silicon yield issues and you can not do anything about it. (That's a foundry problem.)
Put design margin into the analog part in the form of noise margins in the design and architecture items to deal with gain and offset limitations.
At the end of the day to put that design margin in, you probably became 7% of the chip area, and upped the current a little bit (think noise margin and impedance scaling).
But, again for the sake of argument lets say your yield at final test goes from 70% to 95%, and that last 5% of loss is due to wafer defects and the chip being so big.
Who is Jeff?