Hi Stephan/All
Re-activating this thread since I am still confused. sorry!

This is how I do "practical" design. Lets see our offset spec if 10mV.
I will take the worst case PVT corners and run MC on that. If you have designed circuits you know what offset depends upon so you know what is the worst case corner.
I will run as many MC samples as needed till my offset doesn't change appreciably. So for instance I run 200 samples I see my max offset is 4mV at slow corner. I run 400 samples I see max offset is 6mV. I run 500 samples and I see it at 6.2mV. I will basically say I am done since I am far from spec.
If I am close to spec (say spec was 6.5mV), I will increase device size to get some more margin. Engineering judgement (no science)

Now what is wrong with this approach ?

Jeff
Sorry. I don't understand your response.

We are trying to make a design of ADC (say) with high yield so you don't have to throw your SoC away.
Are you saying forget about sizing - just make it huge so that you don't have to worry about meeting spec?

carlgrace wrote on Jul 22^nd, 2014, 10:45pm:


Agreed!

Lets take the case of some big SOC where the ADC/DAC/PLL/Whatever occupies 5% of the chip area and the other 95% of the chip is a big pile of digital verilog.

2 things will kill this IC:

1 - defect density statistics in the digital parts.
2- analog parts not operating within spec (noise, offset, whatever)

Defect density is pure statistical silicon yield issues and you can not do anything about it. (That's a foundry problem.)

Put design margin into the analog part in the form of noise margins in the design and architecture items to deal with gain and offset limitations.

At the end of the day to put that design margin in, you probably became 7% of the chip area, and upped the current a little bit (think noise margin and impedance scaling).

But, again for the sake of argument lets say your yield at final test goes from 70% to 95%, and that last 5% of loss is due to wafer defects and the chip being so big.

Who is Jeff?

Lex wrote on Jul 29^th, 2014, 7:53am:


If you go that path the product will be obsolete before you are out the door with it.

Frequently the design cycle is happening before silicon actually exists. I was doing designs on 45nm when the actual existence of any real 45nm wafers was about 6 months in the future.

That's how this business works...

How good are these statistical models you are using folks?

Results are only as good as the model being used.

Maybe I'm misunderstanding you, but the way I interpret your comment is like: we'll do what we can to improve yield qualitatively (e.g. some growing here and there, alignment here and there, etc.) and then just shoot and hope for the best (yield).

The problem I have with that is that it sounds like a 'slippery slope'. Growing some circuit is fine, but where to stop? Same for alignment circuits etc. At a point, I'd question myself, is it a matter of diminishing returns or does the yield still significantly improves? Then comes the logical (to me at least) question: how can I verify whether it still make sense?

I share your skepticism on models, simulated accuracy etc. and I think that it is important. But I don't share the opinion that their results are lost in noise. For example, a simple corner in an ADC like a SF, Cmax is also a high sigma event, but I bet you still take in consideration, don't you?

Contrary to Lex's obvious assumption I think it needs to be said that trim circuits can save design time and money.

I used to work at a well-known, large analog IC manufacturer and we always added trim bits because we knew that the "corners" were mostly hogwash.  

With TSMC, we almost always got very close to nominal, no worries.  Every once in a while we got some screwy wafers.  I evaluated dies from different wafer runs for a communications SOC I was working on and while I saw a bit of variation I didn't see anything to convince me that there were any Gaussian processes at work there.

I think the idea that you can add trimming bits and go from 2.8sigma yield to 4.2 sigma yield at 90% is a meaningless statement devoid of any purpose.

Want to design a successful chip cheaply on an accelerated schedule?  Design for nominal, put in some margin so it doesn't fail at the most likely corners, and put in some trim bits that can be set during wafer sort or through SPI/I2C.

Also, I'm very interested in your last sentence, Lex.  Have you ever actually seen a wafer exhibit anything close to a SF corner?  Can you suggest any physical effect during wafer fab that could yield such a unicorn?

Image sensors are really not a good place to look at this. When you look at the output of an image sensor, nothing lines up until you run a software image calibration (White-Black and the Bayer color balancing)

Consequently with image sensors you are putting a LOT of calibration and alignment into the game, as a function of the image processing software.

So Lex, sorry but you got the trim and calibration system there already.