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Design flow for high yield (Read 862 times)
Lex
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Eindhoven, Holland
Re: Design flow for high yield
Reply #30 - Aug 13th, 2014, 2:46am
 
Sigh.. point was not whether to implement or not. It was about justification by quantification.

Sure we have alignment circuits on chip. We can turn them on/off. We know the costs in terms of performance, but also the benefits. There have been cases where total performance was better when turned off, so that's why its verified on and off.

May I ask what kind of Cpk you guys got back from your designs/chips?
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