Hi all, I’m now designing a unity gain sampling buffer, as shown in the attached figure. The differential amplifier is just a simple single stage amplifier with PMOS current sources load. I’m aiming for 1% static error, which resulting in the following design specs:
Av=112
GBW=11.7MHz
CL=150fF (@each output node of the differential output)
Sampling cap CH=70fF
Power: 1.2V*455nA (each branch)
The size of input NMOS are 2.48u/660n (0.18um technology), input capacitance is about 5fF


However, the final static error is 11.7mV/499mV=2.3% > 1%. At static state, the differential input voltage is 4.88mV, giving 4.88mV/499mV=1% static error, which is in line with what I expected. Therefore, the question is where is the rest 11.7-4.88=6.8mV error from?

In order to check if the error is from switches, I replace the amplifier with a veriloga model with the same specs shown above. The simulation showed that there was only 1% static error caused by finite gain, which perfectly match with the theory analysis. Therefore, the extra error should come from the amplifier.

A further guess is the input capacitance Cin of the amplifier. Taking into account the ratio x=Cin/CH, the static output is Vo[1-(x+1)/Av]. I do find the simulation results are in line with this equation, i.e., the error decreases with respect to CH, and increase with respect to Cin (adding cap at input nodes). Moreover, the simulation relationship between the error and CH indicates that Cin is equal to 80fF. However, Cin is only 5fF in my circuit, which means the error caused by Cin is almost neglectable .

Therefore, in short, my question is whether the input capacitance is the reason for the extra static error? If no, what are the possible reasons?

Thanks a lot.

Hi Yawei

The setting time is about 120ns. Here is the simulation results. The differential inputs and outputs are shown in the left. In the right figure, Vinp Vinn are input, inp and inn are the input node of amplifier, and outp and outn are output.