It is not wise to state something like that. The circuit has to be known before deciding the worst case corner. Also a circuit has many worst case corners. It depends on what performance metric are you focusing to.

hello,
as every one pointed out it depends on bias and more imp is parameters of imp.

1.low vdd, slow nmos and pmos, low temp will be the worst case of a frequency divider, but this works pretty well for BW of high speed buffers.....
2. slow nmos and fast pmos or slow pmos and fast nmos  will be the worst case for offset...

Thanks,
Raj.