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The Designer's Guide Community Forum › Design Languages › Verilog-AMS › need solution for following error in rtl synthesis tool in cadence
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need solution for following error in rtl synthesis tool in cadence (Read 1845 times)
aathi27
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need solution for following error in rtl synthesis tool in cadence
Mar 06th, 2013, 1:49am  
reg [7:0]cb[3:0][3:0];
                    |
Error   : Verilog-2001 feature. [VLOGPT-3] [read_hdl]
       : Multiple dimensions in file './sad.v' on line 8, column 22.
       : The design must be read in with 'read_hdl -v2001'.
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Geoffrey_Coram
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Re: need solution for following error in rtl synthesis tool in cadence
Reply #1 - Mar 6th, 2013, 5:17am  
Did you read the error message?  It says you have to specify -v2001 because you're using a feature that is from a later version of the language than your simulator supports by default.
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