raja.cedt
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Hello Sharath, how do you know that they are not integrating?? in fact They do. This depends on many things 1. When someone want to build complete system they have to integrate but people want to test first ADC without any further complications.
2. For example few ip companies sell only ADC ip, that means when you are going to buy and integrate with your system i am sure you will have some where one clock internal (if it is a high speed say few GHz) or very few external crystal clocks (around 100MHz which is typically called a system clock )
3. For a product people don't like integrate more than 1 PLL of course with some divider to satisfy all the blocks clocking requirements.
4. In fact forcing some external clock through a bond pad after 2GHZ is very difficult, even if you could manage to force through a strong driver still you will be limited by jitter, even on top of this this can coupled to supply though bond wire coupling.
5. Please refer the following pap in which they have integrated PLL. a. A 15mW 3.6GS/s CT-ΔΣ ADC with 36MHz Bandwidth and 83dB DR in 90nm CMOS b. A 14b 20mW 640MHz CMOS CT ΔΣ ADC with 20MHz Signal Bandwidth and 12b ENOB
6. Please have a look on attached fig and please note that this is my view, since i am not an ADC designer you are most welcome to correct if any thing wrong.
Thanks, Raj.
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