Hi All,

I am working on Delay locked loop design for 200MHz clock.
Using Maneatis architecture. I have some doubt related to design,
please help me regarding this :
1. What does it mean by symmetric load.
2. How to size (W/L) of the symmetric load.
3. It's is said that swing will be symmetric at VControl/2 . but in my design i am not getting this.

please help....

saurabh3488,

Without analyzing it, the circuit you have shown appears to be a way of implementing a PMOS active load.  I think the traditional implementation would require a separate bias branch and common mode feedback, but in this case neither seems to be required.

Hope this helps.

Tim