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Delay Locked Loop Design (Read 3722 times)
saurabh3488
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Delay Locked Loop Design
Apr 24th, 2013, 4:36am
 
Hi All,

I am working on Delay locked loop design for 200MHz clock.
Using Maneatis architecture. I have some doubt related to design,
please help me regarding this :
1. What does it mean by symmetric load.
2. How to size (W/L) of the symmetric load.
3. It's is said that swing will be symmetric at VControl/2 . but in my design i am not getting this.

please help....
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saurabh3488
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Re: Delay Locked Loop Design
Reply #1 - Apr 24th, 2013, 4:37am
 
V-I curve of symmetric load.

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tm123
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Re: Delay Locked Loop Design
Reply #2 - Jul 22nd, 2013, 9:24am
 
saurabh3488,

Without analyzing it, the circuit you have shown appears to be a way of implementing a PMOS active load.  I think the traditional implementation would require a separate bias branch and common mode feedback, but in this case neither seems to be required.

Hope this helps.

Tim
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