Hello,
Before asking for help, I would like to present the situation a little.
I'm working on an amplifier. The amplifier is working fine, but there is a problem. My supply voltage is 5V and the transistors I use to amplify can only sustain 3.3V.
During power up, I fixed this voltage issue by using a cascode.
However, during power down, I have no current in my cascode current mirror, so my cascode doesn't shift the voltage anymore, and several transistors are now exposed to 5V (voltage between drain and source for instance).
Please find my simplified schematic in the following pdf file :
http://www.pdfhost.net/index.php?Action=Download&File=b46298d3d8a7de2500262eb3f1...So, the problem is for instance, Transistor 1 (next to INPUT). During power down, the drain is at 5V and the source is at 0V.
I tried to find solutions, but everything I found wasn't validated because I've been told that with such low current, simulations are not reliable (or at least we can't reproduce it on sillicon).
My question is the following, how would you deal with this issue? knowing that, as I am in a power down state, consumption should be minimal. I have no strict restriction on surface of sillicon but I don't think a LDO to shift the voltage from 5V to 3.3V is acceptable (for instance).
I tried to find something on google, but nothing come up, I don't even know which key words to use.
Thank you for your help!