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determine PLL requirements for ADC (Read 2339 times)

aaron_do Senior Fellow Offline Posts: 1398	determine PLL requirements for ADC Jun 30^th, 2013, 11:52pm Hi all, I'm starting a new position doing mixed-signal design. So far I've only worked in RF/Analog. I need to know how I can calculate PLL requirements for a baseband ADC based on modulation/sampling rate etc. Does anybody have any good links? thanks, Aaron
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raja.cedt Senior Fellow Offline Posts: 1516 Germany	Re: determine PLL requirements for ADC Reply #1 - Jul 1^st, 2013, 5:26am hello, In-general cycle to cycle jitter matters for an ADC, because error in the sampling time instant will leads to SNR drop. The following pap has some points .... 1. Specification Driven Design of Phase Locked Loops 2. http://www.maximintegrated.com/app-notes/index.mvp/id/800 Thanks, Raj.
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aaron_do Senior Fellow Offline Posts: 1398	Re: determine PLL requirements for ADC Reply #2 - Jul 1^st, 2013, 6:27pm thanks Raj. Aaron
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