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conditional component use? (Read 2021 times)
perchick
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conditional component use?
Jul 02nd, 2013, 7:18am
 
Hi
im new here, hope this is the right place for this type of questions

im writing a tic tac toe checker and i was wondering if i could get some help about conditions outside a process.

i just wanted to say that I've already wrote this code using a procedure but i wanted to learn how to do this with components

this is just the start of the code, when ill understand how do i work outside a process ill write the rest

the rules are: d_in is 2 bit vector who writes the board. "00" and "11" has no affect (they do but it's not relevant for now), "10" is o_win, "01" is x_win.

my code so far:

Code:
library ieee;
use ieee.std_logic_1164.all;
use work.TicTacToe.all;	---package woth type state (x_win, o_win, no_win, idle)

entity FSM is
port (	d_in : in std_logic_vector (1 downto 0);
		PS : in state;
		NS : out state := idle);
end FSM;

architecture arch_FSM of FSM is

begin

		process (PS, d_in)
	begin
			case PS is
					when idle =>
						--result <= "00";
						if d_in = "01" then
							NS <=x_win;
						elsif d_in = "10" then
							NS <=o_win;
						else
							NS <= idle;

						end if;
					when x_win =>
						--\result <= "01";

							if d_in = "10" then
								NS <= no_win;
							else
								NS <= x_win ;
							end if;
					when o_win =>
						--result <= "10";

							if d_in = "01" then
								NS <= no_win;
							else
								NS <= o_win;
							end if;
					when no_win =>
						--result <= "11";

					when others => NS <= idle;

				end case;
		end process;


end architecture;

library ieee;
use ieee.std_logic_1164.all;
use work.TicTacToe.all;

entity x_o is
port 	(d_in 	: in std_logic_vector (1 downto 0);
		 clk, rst_n	: in std_logic;
		 stts		: out  std_logic_vector (1 downto 0));
end entity;

architecture arch_x_o of x_o is
component FSM is
port (	d_in : in std_logic_vector (1 downto 0);
		PS : in state;
		NS : out state);
end component;
signal row_status	: state := idle;
type matrix is array (0 to 2) of state;
signal mem	: matrix	:= (others => idle);	--memory reg for column check. every index will be a state by itself
signal temp : state := idle;
signal NS 	: state := idle;
signal i	: integer := 0;
begin

	temp <= mem (i); --why can't i just use mem (i) in the component?, for some reason i cant do that.

	u1 : FSM port map (d_in, row_status, row_status);
	u2: FSM port map (d_in, temp, NS );
	-- if this was sequential I would insert NS into mem (i) and   advance i for next check
	-- if I use a process for that with d_in and clk in the sensitive list and advance i
	-- for every change in d_in and rising_edge ill get the the component is been used twice
	--befor i advance and after
	-- i wonder if i can do all that outside a process since the component has a process in him
end architecture; 

 

my problems with this are mentioned in the code
hope someone can explain how do i work outside a process
thanks in advance
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