aaron_do wrote on Jul 9th, 2013, 5:47pm:Hi Tim,
thanks for the advice. Actually I tried implementing a VCO+ divider with a nonlinear Kvco, and although the settling time was about the same, the transient curve of the control voltage was not the same.
Anyway for my application, the PLL is quite simple, and its possible to complete the transient analysis overnight. I just wanted to see if it were possible to run the simulation even faster.
regards,
Aaron
Overnight is not surprising
All behavior PLL (I've done these in Verilog AMS) will close and run in 20 mins, but no transistors. Depends a lot on your divide ratios, where the Fvco >> Freference the closed loop runs can take a while.