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aaron_do

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Best way to bias my ring VCO
Aug 20^th, 2013, 1:24am

Hi all,

My question is, what is the best way to bias my ring VCO? The differential pair is resistor loaded. Here is the problem...

1. The supply is coming from an LDO which is referenced to the bandgap voltage. However the bandgap is a bit noisy, so that means my supply is also noisy. Therefore I need good supply rejection.

2. From 1, I decided to bias the VCO using a current source. However, the current source is also referenced to the bandgap voltage, so the situation isn't really improved.

I've come up with some preliminary solutions, but they're not ideal.

1. Heavy filtering on the bandgap. I can do this but the layout area is large, and the startup time is long.

2. Generate the bias current locally. Since I need good supply rejection, I guess I need to design a bandgap. It should be higher power than the original so that I get better noise performance. Actually even with an ideal bandgap, my VCO doesn't have very good power supply rejection anyway due to the limited headroom.

So does anybody have any suggestions on how to make sure my noise performance is not limited by the bandgap?

thanks,
Aaron

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tm123

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Re: Best way to bias my ring VCO
Reply #1 - Aug 20^th, 2013, 6:57am

Hi Aaron,

Sometimes LDO's have a really large cap that serves as dominant pole compensation and provides filtering of the output voltage, is that not an available option in this case?

What is the frequency of your ring VCO and are you designing with bipolar or MOS? If you are designing with MOS, maybe you can try using a PMOS current source and PMOS differential pair. The PMOS current source should provide you some supply rejection. If you are designing with bipolar at high speed, this may not be an option because pnp's are generally not as fast as npn's.

Hope this helps,
Tim

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raja.cedt

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Re: Best way to bias my ring VCO
Reply #2 - Aug 20^th, 2013, 7:42am

Dear Aaron,
are you talking about power supply noise or thermal noise? If you have thermal noise then large loop filter or redesigning would help, but i am no so sure since you are using differential pair as delay element whatever supply noise you have should be appeared like common mode noise, will have less impact on phase noise.

If you have problem with power supply noise Please use self bias biasing rather than a constant bias or some thing else.

Thanks,
Raj.

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aaron_do

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Re: Best way to bias my ring VCO
Reply #3 - Aug 20^th, 2013, 11:38pm

Hi guys,

thanks for the replies. The root of the problem is that the only reference I have (the bandgap) is noisy. So if I design a current-source, I get a noisy current that gets up-converted. If I just use a resistor, the power supply noise appears directly across the resistor which is the same this as a noisy current source, so back to square 1.

Quote:

Sometimes LDO's have a really large cap that serves as dominant pole compensation and provides filtering of the output voltage, is that not an available option in this case? �

the problem is it would have to be a really large cap to be effective. The noise performance is critical just outside my loop bandwidth (around 4 - 10 MHz). Beyond 10 MHz, I guess the noise shaping of the VCO makes the supply noise insignificant.

Quote:

If you are designing with MOS, maybe you can try using a PMOS current source and PMOS differential pair. �The PMOS current source should provide you some supply rejection.

The question is what is my current source referenced to? The noise originates from the BG reference, so if my current source is referenced to the BG reference then the situation isn't improved.

Quote:

are you talking about power supply noise or thermal noise?

Its power supply noise, but because the power supply is from an LDO referenced to the bandgap, its basically the bandgap noise. My main concern is low-frequency noise being upconverted.

Quote:

If you have thermal noise then large loop filter or redesigning would help

sorry I don't understand your meaning. I can't increase the loop bandwidth because its already about 1/10x the reference frequency.

Quote:

whatever supply noise you have should be appeared like common mode noise, will have less impact on phase noise.

The power supply noise is affecting my current bias because the limited headroom means my current bias has poor Rout. So the low-frequency supply noise is modulating my current bias and it then gets differentially up-converted and appears as phase noise.

Quote:

Please use self bias biasing rather than a constant bias or some thing else

What do you mean by self-biasing? For instance instead of a current source, use a resistor? I have tried this but it is even worse as it is even more sensitive to the power supply.

thanks,
Aaron

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tm123

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Re: Best way to bias my ring VCO
Reply #4 - Aug 21^st, 2013, 6:37am

Hi Aaron,

OK, I see the issue now. If you have access to a Gray/Meyer book check the section on Self Biasing (4.4.2.3 in the 4th edition text). I have used the 'threshold referenced current source' circuit in the past with good success. You can actually cascade them to get better power supply rejection, I would recommend putting at least 2 stages. If you don't have access to the text I will try to upload a pic.

Tim

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aaron_do

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Re: Best way to bias my ring VCO
Reply #5 - Aug 21^st, 2013, 7:47am

Hi Tim,

Thanks for this. I was actually trying to remember where I had seen a circuit like this. Anyway its an interesting circuit, but do u think its better than a bandgap for supply rejection? As I mentioned earlier, one option is to have a local bandgap for the vco reference. One problem which isnt addressed is that the vco tail current has pretty poor output impedance due to the limited headroom. Perhaps I need to work on improving that more.

Thanks,
Aaron

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tm123

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Re: Best way to bias my ring VCO
Reply #6 - Aug 21^st, 2013, 8:31am

Hi Aaron,

You have a good point about the current source output impedance, perhaps low output impedance is leading to more upconversion of low frequency bias noise. I could be wrong about that though.

Are you designing in a BiCMOS or CMOS process? Depending on how much power you can use, low noise bandgap design can be difficult. When you say bandgap, I imagine something like a Brokaw cell or PTAT generator (if npn's are available) or a standard CMOS bandgap that uses substrate pnp's and an op amp (if npn's are not available). Of course there are other variations, but I think it would be interesting to compare the noise performance of a more traditional 'bandgap' to the self bias circuit referenced in Gray/Meyer. One stage of the self bias circuit may not be sufficient for power supply rejection, but you can cascade them. I would expect two or three stages to have enough power supply rejection for most applications.

Tim

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aaron_do

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Re: Best way to bias my ring VCO
Reply #7 - Aug 21^st, 2013, 5:44pm

Hi Tim,

I'm designing in 40nm CMOS. So the transistors have poor Rout, and the supply voltage is limited. I do have some options, but because I inherited this design, my manager is reluctant to let me make major changes (I can understand that).

I was talking about something like a low-voltage version of a Brokaw cell. In terms of noise performance, I'm not sure which would be better, but I know they would both be better than what I have now. The reference I have at the moment is generated from very low DC current, so its SNR is poor.

I'll give the circuit a try.

thanks for the help,
Aaron

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tm123 Community Member Offline Posts: 67 Chicago, IL	Re: Best way to bias my ring VCO Reply #8 - Aug 22^nd, 2013, 6:19am Aaron, I do not have any design experience in 40nm CMOS, but at 65nm is was almost always a must to use cascode current sources for good Rout. Good luck, let me know how it goes. Tim
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aaron_do Senior Fellow Offline Posts: 1398	Re: Best way to bias my ring VCO Reply #9 - Aug 22^nd, 2013, 7:51pm Thanks for the tip. Just not sure if I have the headroom... Aaron
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carlgrace Senior Member Offline Posts: 231 Berkeley, CA	Re: Best way to bias my ring VCO Reply #10 - Aug 26^th, 2013, 3:57pm Do you have a pin available to externally filter the bandgap voltage before you use it? If not, can you put an RC filter before the LDO? Are you using a mixed-signal process so you have the ability to use MIMCAPs? If not you can use MOSCAPs but be sure to use the thick oxide devices.
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aaron_do

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Re: Best way to bias my ring VCO
Reply #11 - Aug 26^th, 2013, 5:46pm

Hi,

thanks for the reply. As I did not design the LDO, I can't directly make changes. But I have been asking the project manager to have filtering in front of the LDO. We have been playing around with the idea of using a big off-chip cap, but it would definitely affect the start-up time.

I'm using a combination of MOMCAPs and MOSCAPs (I/O device).

thanks,
Aaron

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