The impact of sample clock jitter on ADC SNR is well described in many papers can be found by google.

However, I never see discussion covering one case that puzzles me:

when the jitter is a narrow band (< 1MHz) gaussian noise and input signal is a sin wave. The ADC output is essentially the PSD of the sampling sin clock with its phase noise.

Since ADC's output is discrete, its PSD is plotted after FFT processing.

My question is: if the FFT bin size is larger or comparable to the bandwidth of phase noise, then all the noise may fall into this signal bin and the result may appear to be jitter free.

Any thoughts? Is my concern valid?