Hi all,


I have designed a divide by 2 using a single DFF with Qbar fed back to the input, and found that it has a minimum frequency of operation (around 1 MHz). Below the minimum frequency of operation, the output oscillates at the clock rate instead of half the clock rate. Is this typical? The DFF uses dynamic logic. Also, is there a more robust way to design the DFF so that it doesn't face this problem?

Each latch looks something like this:


--------|Clocked INV>---------------|INV>--------------------->
                   ↑               |                                     |
                   |               |                                     |
                   |               |                                     |
                 CLK            |-----<Clocked INV|--------|
                                                    ↑
                                                    |
                                                    |
                                                  CLKB


thanks,
Aaron