hchanda
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Hi all,
I am working on a LDO which as PMOS as it's pass transistor. This regulator has output load cap that can vary from (1uF to 8uF) which is big. I have a single stage amplifier output driving the pass transistor. I am trying to compensate the LDO using miller cap, which does not seem to help.
In the above structure I described above, before compensation the dominant pole is at output (near output load cap) and the next pole is at the output of the amplifier.
When we apply miller cap does it push the pole at the output of error amplifier to lower frequencies and the pole at the output (near cload) does not move much because of huge capacitance (1uF). Doesn't this worsen the LDO compensation because now miller is actually pushing poles together?
I also need some good understanding on the miller compensation I read a paper "re examination of pole splitting of generic single stage amplifier". This paper states that miller cap actually pushes the dominant pole to lower frequency and non dominant pole to higher frequency, whether your dominant pole is at input or output. Is this true? I always thought that miller cap always pushes the pole at the input to lower frequencies and the pole at the output to higher frequency. Can anyone clarify on this and explain me intuitively?
So again back to LDO compensation, if the LDO has to drive large capacitive loads, does miller compensation work very well? Any other better and simple techniques to achieve good stability.
I found couple of papers on compensating the LDO (still going over them), none of them discusses the cons of using miller compesation in detail.
Appreciate your time and response.
Thanks
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