Kotesh
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In verilog design, we have ?: operator and if..else statement.
for ex: c = foo ? a:b for ex: if (foo) c = a; else c = b;
which one of the above code is preferable in verilog design prospective
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and what is the difference between them.
Shall i use ?: operator in design rather than if..else . If Yes, why?
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