hi analog_geek,

1. mainly engineering trade off. pmos input has lower flicker noise, nmos has higher bandwidth generally. then there is the issue of input voltage levels (i'll let you figure this one out).

2. you can read this up in almost any ic text book

3. generally yes ... but there many other ways to do this.

4. magic ... or some may say semiconductor physics.

i think you may find the berkeley webcast courses very good in getting you up to speed ... try looking at this course ...
Electrical Engineering 105, 001 - Spring 2013

http://webcast.berkeley.edu/playlist#c,d,Electrical_Engineering,-XXv-cvA_iApSM93...

good luck !

Hi,


1. Are you implying that you can use an NMOS current mirror with an NMOS diff pair?

2.Yes. Both transistors have high output impedance on their drain side. So PMOS is a good source and NMOS is a good sink. Current sources need high output impedance.

3. You could use an NMOS with an NMOS diff pair if you want. I believe you get better PSRR using a PMOS with an NMOS diff pair since at high frequencies, but I'm not sure if there's another main reason.

4. Because of the VT requirement to turn on a transistor...


Aaron

Hi,


the PMOS and the NMOS are physically different. For the PMOS, the source is at a higher potential than the drain, and for an NMOS, the drain is at a higher potential than the source. That defines the drain and source. Furthermore, a high impedance is seen looking into the drain and a low impedance is seen looking into the source. Because you need a high impedance to mimic a current source, a PMOS naturally forms a source, and an NMOS naturally results in a sink. Does that help? I'm not sure if I'm getting your question.

Assuming the transistor is turned ON, there will be a VT drop from the gate to the source. Hence the level shifting. Also, a source follower has an AC gain of 1 due to the inherent negative feedback in the structure. Unless you're asking about device physics, I'm not really sure what else you want to know...


Aaron

Hi,


I didn't exactly follow what your professor meant there. Maybe he misunderstood your question.

Anyway, for a NMOS diff pair, and a PMOS current mirror, in order to get the best possible matching between your diff pair devices, you would want the drain voltage of the two PMOS transistors (the current mirror) to be equal (you do that by properly sizing the PMOS transistors). A result of this is that when a PMOS is used in the subsequent stage, it is effectively "mirrored" over. It is not a true current mirror because it only works at the quiescent operating point, but the design becomes easier. For example, in your picture, VDQ4 =  VGQ3 = VDQ3 to get the best matching in your diff pair. Therefore, VGQ6 = VGQ3 (only at the operating point).

Also, because a PMOS mirror is used, there is only one diode drop from the supply to the output of the diff pair. Therefore, the voltage at the output of the diff pair is a little high to connect an NMOS to. Your NMOS might end up in the triode region. Its just a little trickier to design. For example, one diode connected PMOS drop might be 0.8 V. For a 2.5-V supply, that would make the DC level at that point equal to 1.7 V. If you connect an NMOS gate directly to that, and your output DC level is 1.25 V, then your device is operating a little close to the triode region. It could show up in your common-mode range.

As I pointed out earlier, I believe you get better PSRR using a PMOS. Its difficult to explain, so I'll leave it to you to analyze if you're interested.


Aaron

Hi,


It's more like if there is any cap from the supply to the gate of the second stage, then at high frequencies, the gate of the second stage will follow the supply. So for a PMOS, VGS = 0, so the device's current is not modulated by the supply.


regards,
Aaron

tm123 wrote on Oct 30^th, 2013, 10:24am:



Thats awesome.. so u mean when we use pmos in second stage of OTA, then as source of PMOS is connected to VSS and its gate is at higher potential .so that VGS will be small enough to keep PMOS in saturation ..while on the other hand if u use NMOS in second stage of OTA, then its VGS will be higher as source is at lower potential compare to PMOS source so that its VGS is high..this will cause nmos to be worked in triode region.
Is that correct?