Hi,

I have used a OpAmp based comparator in one of my designs.  The first file is the circuit. Second and Third are the plots of the comparator inputs and output.. In that, the first sub window is the output of the comparator. Second and third sub- windows are the positive and negative input of the comparator. Though I am varying the inputs to the comparator, I don't see the expected behavior. Though inputs are varying around 1V and there is a significant difference between their inputs, my output is always around 500mV. Can you pls help me out why it is behaving so?

Do you have a reasonable matching? If the second-stage transistors size is unreasonable. The output may be stuck even there are input difference.

Mikay

can you post device sizes ?

I just tried the circuit topology on 0.18um and it looks ok.
(I won't bias it this way though !)

So most likely due to your current biasing scheme and device sizing as mentioned by Mikay and boe.