Hi Aaron,
Thanks a lot for your reply! Your reply give me a lot of hint, I actually have checked my layout carefully. Fortunately I didn't find any especially latchup.
But to update, I finally get a way to prevent the chip from keeping breaking down, that is, put a current-limiting resistor in series, between DC source and pad of Ibias. So I guess, the chip breaking down might because an ESD event or something.
As for the voltage at the pin, I don't pay attention on it anymore. instead, I only concern bias current. once bias current reached expected value, the total current from voltage supply reach the expected value too. But, I will keep trying to find the reason for problem (4), because it is still a issue in future bias circuit.
Thank you!
Regards
![Smiley Smiley](https://designers-guide.org/forum/Templates/Forum/default/smiley.gif)
Hao
aaron_do wrote on Jan 20th, 2014, 5:05pm:Hi,
for problem (4), I assume the voltage at the pin (probe the pin itself) is 0.75 V? You should probably check your layout for weak connections in any wire carrying current, particularly the ground and power lines. Also check if there are any diodes that could be turning on (floating bodies for example), or any possibility of latchup.
During your test do you have any input signal, or is it just DC? For problem 5, you mention the circuit suddenly fails. After that, try sweeping the voltage from 0 to 1 V or so. Does it have a turn-on voltage? Maybe its some diode turning on. Also, if you really have a high VDD while the transistor is on for a long period, you could stress the device (HCI).
regards,
Aaron